1. Field of the Invention
The present invention relates to a circuit module including semiconductor ICs mounted on a printed wiring board and, more particularly, to a memory module which achieves an increased signal transfer rate.
2. Description of the Background Art
A circuit module comprises a plurality of semiconductor ICs having the same function and mounted on a printed wiring board in conjunction with a control IC, as required. The most common semiconductor ICs to be mounted include a memory IC. Thus, description will now be given using a memory module as an example.
FIG. 16 is a front view of a conventional memory module 101. A plurality, illustrated herein as four, of memory ICs 103 are mounted on a printed wiring board 102. Each of the memory ICs 103 includes pins DQ0 to DQn which are data pins for inputting and outputting data signals where n is a natural number. For example, n=7 when a memory IC 103 has eight data pins. The reference character DQt (0xe2x89xa6txe2x89xa6n) is used hereinafter to generically represent the data pins. An individual data signal is inputted to and outputted from each data pin DQt of each of the memory ICs 103. Thus, when the four memory ICs 103 each having eight data pins are mounted on the printed wiring board 102 as shown in FIG. 16, 32 (4xc3x978) connector terminals among a plurality of connector terminals 104 of the memory module 101 function as connector terminals 104a for the data signals. The connector terminals 104a and the data pins DQ0 to DQn are connected to each other by interconnect lines 105a provided on the printed wiring board 102. For purposes of simplification, only the connection between the data pins DQ0 to DQn of one of the memory ICs 103 which is positioned at the top of the drawing paper (or the rightmost memory IC 103) and the connector terminals 104 is typically shown in FIG. 16.
Each of the memory ICs 103 further includes pins A0 to Ak which are address/command pins for inputting address signals or command signals (referred to hereinafter together as xe2x80x9caddress/command signalsxe2x80x9d) to each memory IC 103 where k is a natural number. For example, k=7 when a memory IC 103 has eight address/command pins. The reference character As (0xe2x89xa6sxe2x89xa6k) is used hereinafter to generically represent the address/command pins. Unlike the data signals to be inputted and outputted, an address/command signal is commonly inputted to the address/command pins As of the respective memory ICs 103. Thus, when each of the memory ICs 103 includes eight address/command pins as shown in FIG. 16, eight connector terminals among the plurality of connector terminals 104 of the memory module 101 function as connector terminals 104b for the address/command signals. An interconnect line 105b provided on the printed wiring board 102 is connected to each of the plurality of connector terminals 104b. 
FIG. 17 is a sectional view of the memory module 101, and particularly shows the memory module 101 in section as viewed in the direction of the arrow Y1 of FIG. 16. With reference to FIGS. 16 and 17, the connection between the interconnect line 105b and the address/command pins As is described hereinafter. Since the interconnect lines 105a are provided on the printed wiring board 102 as described above, an interconnect line for connecting the interconnect line 105b and the address/command pins As is not permitted to be provided on the printed wiring board 102. For this reason, a lower interconnect line 105c extending in the direction perpendicular to the longitudinal direction of the interconnect line 105b is provided inside the printed wiring board 102, and the interconnect line 105b and the lower interconnect line 105c are connected to each other by a conductor which fills a through hole 106. Interconnect lines 108 for connection to the address/command pins As are provided on the printed wiring board 102, and the interconnect lines 108 and the lower interconnect line 105c are connected to each other by a conductor which fills through holes 107. In this manner, the connection is established between the interconnect line 105b and the address/command pins As. This allows an address/command signal applied to the connector terminal 104b from the exterior to be transmitted in sequential order through the interconnect line 105b, the conductor which fills the through hole 106, the lower interconnect line 105c, the conductor which fills the through holes 107, the interconnect lines 108, and the address/command pins As to the memory ICs 103.
FIG. 18 is a side view of the general configuration of a system including a plurality of memory modules each corresponding to the memory module 101. A signal line 111 is provided on a motherboard 109. The signal line 111 is connected at one end thereof to a controller 110 disposed on the motherboard 109, and is connected at the other end thereof to a terminating resistor 112 provided on the motherboard 109. The terminating resistor 112 is connected to a power supply 113 for providing a termination potential. A plurality of connectors 114 arranged at regularly spaced intervals in the longitudinal direction of the signal line 111 are provided also on the motherboard 109. The connectors 114 function to physically support the memory modules 101 inserted therein. The insertion of the plurality of memory modules 101 in the respective connectors 114 causes each of the plurality of memory modules 101 to be placed in an upright position, or to extend in the direction perpendicular to the longitudinal direction of the signal line 111. It should be noted that a connector 114 in which no memory module 101 is inserted as shown in FIG. 18 is present in some cases. The connectors 114 also function to establish electrical connection between the connector terminals 104 (not shown in FIG. 18) of the memory modules 101 and the signal line 111. Thus, the data signals and address/command signals outputted from the controller 110 are transmitted through the signal line 111 and the connectors 114 to the memory modules 101. The symbol d shown in FIG. 18 denotes the spacing (pitch) between adjacent memory modules 101.
FIG. 19 is a sectional view of the connector 114 with the memory module 101 inserted therein, and particularly shows the memory module 101 in section as viewed in the direction of the arrow Y2 of FIG. 16. The interconnect line 105a and the data pins DQt are illustrated in FIG. 19. A connector pin 115b and a conductive connector pin 115a which are on opposite sides of the memory module 101 hold the memory module 101 therebetween, thereby to support the memory module 101 in the connector 114. Electrical connection between the signal line 111 and the connector terminal 104a is made through the connector pin 115a. 
With the increase in processor operating speeds, there has been a need to increase the signal transfer rate of the memory modules. Unfortunately, the conventional memory modules 101 described above present drawbacks to be described below in terms of the increase in the signal transfer rate, and are not capable of responding the need.
One of the drawbacks is as follows. The data signals must be synchronized when inputted to and outputted from the data pins DQ0 to DQn of the memory IC 103. In the memory module 101 shown in FIG. 16, however, there is a significant difference in length between an interconnect line 105a0 connected to the data pin DQ0 and an interconnect line 105an connected to the data pin DQn, for example. If the data signals inputted from the controller 110 to the memory IC 103 are synchronous with each other on the signal line 111, the difference in length between the interconnect lines 105a causes the synchronism to be lost, resulting in phase differences between the data signals at the time the data signals are inputted to the memory IC 103. Similarly, if the data signals outputted from the data pins DQ0 to DQn of the memory IC 103 are synchronous with each other, the difference in length between the interconnect lines 105a causes the synchronism to be lost, resulting in phase differences between the data signals on the signal line 111. A difference of 1cm in length between the interconnect lines 105a produces a time difference (skew) of about 70 ps. The skew of 70 ps is not negligible in view of the fact that 1 ns is required for one cycle at a signal transfer rate of 1 gigabit/second for each pin.
Another drawback is as follows. It is assumed that the connector 114 and the memory module 101 are disregarded for consideration of the characteristics of the signal line 111. The characteristic impedance Z0 of the signal line 111 is given by                               Z          0                =                                            L              ·              d                                      C              ·              d                                                          (        1        )            
where C is the capacitance of the signal line 111 per unit length, and L is the inductance of the signal line 111 per unit length.
On the other hand, if the connector 114 and the memory module 101 are taken into consideration, the connector pin 115a and the interconnect line 105a are regarded as stubs branching off from the signal line 111. FIG. 20 is a circuit diagram of an equivalent circuit in this case. Since the wiring capacitances of the stubs and the input capacitance of the memory IC 103 (both referred to hereinafter together as xe2x80x9cstub capacitancesxe2x80x9d in some cases) function as capacitive loads for the signal line 111, the signal line 111, in this case, has a characteristic impedance Z1 given by                               Z          1                =                                            L              ·              d                                                      C                ·                d                            +                              C                C                            +                              C                LF                            +                              C                IN                                                                        (        2        )            
where CC is the wiring capacitance of the connector pin 115a, CLF is the wiring capacitance of the connector terminal 104a and the interconnect line 105a, and CIN is the input capacitance of the memory IC 103.
The resistance of the terminating resistor 112 shown in FIG. 18 must be equal to the characteristic impedance Z1 of the signal line 111 for the purpose of impedance matching for prevention of signal reflection. It will be found from Equation (2) that since the wiring capacitance CC is particularly high in the mounting of the memory module, the characteristic impedance Z1 of the signal line 111 is low. Accordingly, the resistance of the terminating resistor 112 is required to be also low for the impedance matching. This results in an increased amount of power consumption. As an example, if the characteristic impedance Z0 expressed by Equation (1) is 75 ohms, the characteristic impedance Z1 of the signal line 111 for transmitting the data signals is reduced to about 35 ohms due to the mounting of the memory module 101. For the signal line 111 for transmitting the address/command signals, the wiring capacitance CLF and the input capacitance CIN are also high since the plurality of memory ICs 103 are connected to the interconnect line 105b. As a result, the resistance of the terminating resistor 112 is required to be lower, rendering the problem of the increase in power consumption more serious. To solve the problem, it is theoretically possible to increase the characteristic impedance Z1 by increasing the pitch d of the memory modules 101. This, however, decreases a packaging density, and is not a satisfactory solution to the problem in view of such a requirement for computers that a fixed number of memories must be mounted in limited space.
A first aspect of the present invention is intended for a circuit module for insertion in a connector provided on a main surface of a motherboard including first and second signal lines separated from each other at the connector. According to the present invention, the circuit module comprises: a first connector terminal provided on a first main surface of a board and adapted for electrical connection to the first signal line through a first connector pin of the connector; a second connector terminal provided on a second main surface of the board, the second main surface being on opposite side of the board from the first main surface, the second connector terminal being adapted for electrical connection to the second signal line through a second connector pin of the connector; and a first interconnect line for providing electrical connection between the first connector terminal and the second connector terminal.
Preferably, according to a second aspect of the present invention, in the circuit module of the first aspect, the first interconnect line is a conductor that fills a through hole selectively extending between part of the first main surface of the board where the first connector terminal is formed and part of the second main surface of the board where the second connector terminal is formed.
Preferably, according to a third aspect of the present invention, in the circuit module of the first aspect, the first interconnect line is a metal interconnect line provided on a side surface of the board and in contact with both the first and second connector terminals.
Preferably, according to a fourth aspect of the present invention, in the circuit module of the first aspect, the connector includes a plurality of connectors formed on the main surface of the motherboard; a first one of the plurality of connectors includes third and fourth connector pins electrically connected respectively to the first and second signal lines separated from each other at the first connector; the first connector receives an IC module, the IC module having a first main surface and comprising a third connector terminal formed on the first main surface thereof and adapted for connection to the third connector pin, a second interconnect line formed on the first main surface thereof and having a first end connected to the third connector terminal, and a first IC formed on the first main surface thereof and connected to a second end of the second interconnect line, the IC module having a second main surface on opposite side from the first main surface thereof and further comprising a fourth connector terminal formed on the second main surface thereof and adapted for connection to the fourth connector pin, the IC module further comprising a third interconnect line for providing electrical connection between the third connector terminal and the fourth connector terminal; and the circuit module is inserted in a second one of the plurality of connectors, the second connector being not to receive the IC module.
Preferably, according to a fifth aspect of the present invention, the circuit module of the fourth aspect further comprises: a fourth interconnect line formed on the first main surface of the board thereof and having a first end connected to the first connector terminal; and a first capacitive element formed on the first main surface of the board thereof and connected to a second end of the fourth interconnect line, wherein the wiring capacitance of the fourth interconnect line is equal to that of the second interconnect line, and wherein the capacitance of the first capacitive element is equal to the input capacitance of the first IC.
Preferably, according to a sixth aspect of the present invention, in the circuit module of the fifth aspect, the IC module further comprises a fifth interconnect line formed on the second main surface thereof and having a first end connected to the fourth connector terminal, and a second IC formed on the second main surface thereof and connected to a second end of the fifth interconnect line, and the circuit module further comprises: a sixth interconnect line formed on the second main surface of the board thereof and having a first end connected to the second connector terminal; and a second capacitive element formed on the second main surface of the board thereof and connected to a second end of the sixth interconnect line, wherein the wiring capacitance of the sixth interconnect line is equal to that of the fifth interconnect line, and wherein the capacitance of the second capacitive element is equal to the input capacitance of the second IC.
Preferably, according to a seventh aspect of the present invention, in the circuit module of the fifth aspect, the IC module further comprises a fifth interconnect line formed on the second main surface thereof and having a first end connected to the fourth connector terminal, and a second IC formed on the second main surface thereof and connected to a second end of the fifth interconnect line, and the circuit module further comprises: a sixth interconnect line formed on the second main surface of the board thereof and having a first end connected to the second connector terminal; and a third IC formed on the second main surface of the board thereof and connected to a second end of the sixth interconnect line, wherein the wiring capacitance of the sixth interconnect line is equal to that of the fifth interconnect line, and wherein the input capacitance of the third IC is equal to that of the second IC.
Preferably, according to an eighth aspect of the present invention, in the circuit module of the first aspect, the first connector terminal includes a plurality of first connector terminals, and the circuit module further comprises: a plurality of interconnect lines formed on the first main surface of the board thereof and having first ends connected to the plurality of first connector terminals, respectively; and an IC formed on the first main surface of the board thereof and including a plurality of terminals connected to second ends of the plurality of interconnect lines, respectively, the plurality of terminals being arranged in a direction parallel to a direction in which the plurality of first connector terminals are arranged.
A ninth aspect of the present invention is also intended for a circuit module for insertion in a first connector provided on a main surface of a motherboard, the motherboard including a plurality of second connectors provided on the main surface thereof for receiving as required an IC module comprising an IC mounted thereon, a controller provided on the main surface thereof for providing a signal to the IC, and a signal line provided on the main surface thereof and having a first end connected to the controller. According to the present invention, the circuit module comprises: a first connector terminal adapted for electrical connection to the signal line through a first connector pin of the first connector; a first interconnect line having a first end connected to the first connector terminal; a terminating resistor connected to a second end of the first interconnect line, and a power supply for providing a termination potential to the terminating resistor, wherein the signal line is separated at the first and second connectors, wherein the IC module is inserted in each of such ones of the plurality of second connectors that are positioned between the first connector and the controller, and wherein the IC module is not inserted in such ones of the plurality of second connectors that are positioned farther from the controller than the first connector.
Preferably, according to a tenth aspect of the present invention, in the circuit module of the ninth aspect, the IC module further comprises a second connector terminal adapted for connection to the signal line through a second connector pin of each of the plurality of second connectors, and a second interconnect line for providing electrical connection between the second connector terminal and the IC, and the circuit module further comprises: a capacitive element connected to the first interconnect line in common with the terminating resistor, wherein the wiring capacitance of the first interconnect line is equal to that of the second interconnect line, and wherein the capacitance of the capacitive element is equal to the input capacitance of the IC.
An eleventh aspect of the present invention is also intended for a circuit module for insertion in a connector provided on a main surface of a motherboard having a plurality of signal lines. According to the present invention, the circuit module comprises: a plurality of connector terminals formed on a main surface of a board and adapted for connection to the plurality of signal lines through a plurality of connector pins of the connector, respectively; a plurality of interconnect lines formed on the main surface of the board and having first ends connected to the plurality of connector terminals, respectively; and an IC formed on the main surface of the board and including a plurality of terminals connected to second ends of the plurality of interconnect lines, respectively, wherein the plurality of terminals are arranged in a direction parallel to a direction in which the plurality of connector terminals are arranged.
Preferably, according to a twelfth aspect of the present invention, in the circuit module of the eleventh aspect, the IC is a memory IC; the plurality of terminals are data pins for inputting and outputting a data signal; the data pins are provided on a first side of the memory IC which is opposed to the connector terminals; the memory IC further includes address/command pins provided on a second side thereof which is opposite from the first side; and the address/command pins receive an address/command signal through a buffer IC provided on the main surface of the board.
In accordance with the first aspect of the present invention, when the circuit module is inserted into the connector, the first and second signal lines separated from each other at the connector are electrically connected to each other through the first and second connector pins, the first and second connector terminals, and the first interconnect line. That is, the first and second connector pins, the first and second connector terminals, and the first interconnect line are regarded as parts of the first and second signal lines. This reduces the stub capacitance in the circuit module.
In accordance with the second aspect of the present invention, the capacitance of the through hole is lower than the capacitance of the first and second connector pins in the case where the first and second signal lines are not separated at the connector. Thus, the stub capacitance of the circuit module of the present invention is lower than that of conventional circuit modules.
In accordance with the third aspect of the present invention, the wiring capacitance of the metal interconnect line is lower than the capacitance of the through hole of the circuit module of the second aspect. Thus, the stub capacitance of the circuit module of the third aspect is lower than that of the circuit module of the second aspect.
In accordance with the fourth aspect of the present invention, when the first and second signal lines are separated from each other at the connector, the circuit module may be inserted into the second connector, if present, which is not to receive the IC module, to provide electrical connection between the first and second signal lines.
In accordance with the fifth aspect of the present invention, the stub capacitance of the circuit module is equal to the stub capacitance of the IC module. Thus, the fifth aspect of the present invention may hold the characteristic impedance of the first and second signal lines constant throughout the main surface of the motherboard, thereby preventing signal reflection resulting from characteristic impedance mismatching.
In accordance with the sixth aspect of the present invention, in the system wherein ICs are mounted on both the first and second main surfaces of the IC module, the signal reflection resulting from the characteristic impedance mismatching is also prevented, as in the circuit module of the fifth aspect of the present invention.
In accordance with the seventh aspect of the present invention, when one system includes the IC module wherein ICs are mounted on both the first and second main surfaces, thereof and the IC module wherein an IC is mounted on one of the first and second main surfaces thereof, the signal reflection resulting from the characteristic impedance mismatching is also prevented, as in the circuit module of the fifth aspect of the present invention.
The eighth aspect of the present invention may decrease the difference in length between the plurality of interconnect lines to accordingly decrease the difference in wiring capacitance between the interconnect lines. This provides the effect of eliminating the need to consider the individual wiring capacitances of the interconnect lines.
In accordance with the ninth aspect of the present invention, all of the IC modules required by the system are inserted into the second connectors positioned between the first connector and the controller. Only the single circuit module inserted into the first connector may avoid disadvantages resulting from the presence of the second connectors which do not receive the IC modules.
In accordance with the tenth aspect of the present invention, the stub capacitance of the IC module to be inserted into the first connector is equal to the stub capacitance of the circuit modules to be inserted into the second connectors. Therefore, the tenth aspect of the present invention may prevent the signal reflection resulting from the characteristic impedance mismatching as well as providing the effects of the circuit module of the ninth aspect.
The eleventh aspect of the present invention may decrease the difference in length between the plurality of interconnect lines, thereby preventing the generation of skews.
In accordance with the twelfth aspect of the present invention, since the data pins are provided on the first side of the memory IC which is opposed to the connector terminals, the length of the interconnect lines for connecting the connector terminals and the data pins is reduced. Furthermore, since the address/command pins provided on the second side of the memory IC which is not opposed to the connector terminals receive the address/command signal through the buffer IC, the load capacitance of the interconnect line for transmitting the address/command signal is reduced.
It is therefore an object of the present invention to provide a circuit module which suppresses a skew resulting from a difference in length between interconnect lines on the circuit module and provides a low stub capacitance to achieve the reduction in power consumption.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.